1. Field of the Invention
The present invention relates to a semiconductor device, and a semiconductor circuit, a correlation calculation device, a signal converter, and a signal processing system using the semiconductor device and, more particularly, to a semiconductor device which can perform parallel arithmetic operations, a semiconductor circuit using the device, and a correlation calculation device, signal converters such as A/D and D/A converters, and a signal processing system, e.g., a system for processing an image signal, using the semiconductor device.
2. Related Background Art
In a conventional semiconductor device that performs parallel arithmetic operation processing, since the circuit scale increases in progression as the number of signals to be subjected to parallel arithmetic operations increases, the manufacturing cost of the semiconductor device increases, and the manufacturing yield is lowered. Due to an increase in delay amount of a signal transferred through, e.g., wiring lines or due to an increase in the number of times of arithmetic operations in the circuit upon an increase in circuit scale, the operation speed decreases. In addition, the consumption power increases considerably.
The above device will be described by taking, for example, the case of the solid-state image pickup device shown in FIG. 1. In the device shown in FIG. 1, time-series analog signals output from a sensing unit 60, in which image pickup elements 41 are arranged two-dimensionally, and which serves as an area sensor, are converted into digital signals by an A/D converter 40, and are temporarily stored in a frame memory 39. These signals are processed by an arithmetic operation circuit 38, and the processed signals are output from an arithmetic operation output circuit 50. More specifically, by executing correlation calculation between data obtained at different times, the moving amount (.DELTA.X, .DELTA.Y) of an object or the like can be output. The sensing unit 60 of this solid-state image pickup device has many output terminals. The frame memory 39 and the arithmetic operation circuit 38 also have many output terminals. In the solid-state image pickup device in FIG. 1, parallel arithmetic operation processing of signals from these output terminals is performed to shorten the processing time, or the number of processing steps is decreased to reduce the physical circuit scale, thereby increasing the processing speed and realizing real-time processing.
However, in order to perform real-time processing of a dynamic image, the number of arithmetic operations and the number of processing steps in the arithmetic operation processing are very large, and in order to obtain images with higher reality, the circuit scale increases in progression, resulting in a low processing speed. For example, an apparatus which can process an MPEG2 method proposed as a dynamic image expansion/compression method at a practical speed is still under development. The problems of the above-mentioned parallel arithmetic operation processing include not only the problem of a decrease in operation speed but also the problem of an increase in consumption of power upon an increase in circuit scale. In addition, the problem of an increase in manufacturing cost and the problem of a decrease in manufacturing yield upon an increase in circuit scale are posed.
Furthermore, a majority logic circuit effective for the arithmetic operation processing circuit is disclosed in Nikkei Electronics "Economical Majority Logic IC Realized by CMOS", 1973, 11. 5. pp. 132-144. However, this circuit, known is a majority logic circuit as one of the available digital signal processing methods, and is based on a CMOS technique. In this case as well, since the number of elements based on the CMOS technique increases, and the number of stages in the arithmetic operation processing increases, the problems of an increase in circuit scale, an increase in consumption of power, and a decrease in operation speed are similarly posed.